How do I regenerate the Stratix® V Intel FPGA IP for PCIe?

Due to a problem in the Quartus® II software version 13.1 and earlier, you might see the following error when you regenerate the IP for PCIe if you have opened the IP parameter editor without a Stratix® V FPGA project being open.

Error: Simulation model generation failed: <installation path>//sopc_builder/bin/ip-make-simscript --spd=<project path>/<instance name>.spd --output-directory=<project path>/<instance name>_sim

To work around this problem, open or create a Stratix V FPGA project before launching the IP parameter editor.

This problem is fixed in the Quartus II software version 13.1.