Article ID: 000084433 Content Type: Troubleshooting Last Reviewed: 09/11/2012

What is the skew between clocks driven from different PLLs in Altera devices?

Environment

  • PLL
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description Altera® does not specify the skew between clocks driven by different PLLs. Lock times may vary and Altera cannot guarantee that different PLLs will attain lock at the same time. This also applies to the case when the different PLLs are reset at the same time.

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    Stratix® FPGAs