You might encounter this error when instantiating the PLL Intel® FPGA IP with certain output clock phase shift settings.
For example, an ALTLVDS interface with a dara rate of 700 Mbps and deserialization factor of 7, the compilation report shows the output clocks will have 180, 257, and 334 degree phase shifts. However, if you enter these phase shift settings in the PLL Intel® FPGA IP, the parameter editor will report this error.
Enter the phase shift setting as "ps" to replace the degree setting in the PLL Intel® FPGA IP.
This problem is fixed in Quartus® II software version 13.1.