Article ID: 000084343 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why do I get a what-you-see-is-what-you-get (WYSIWYG) error in the Quartus® II software from a Verilog Quartus Mapped (VQM) file generated by Synplify when I have turned off the Synplify mapping option: Disable I/O Insertion?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You may get a WYSIWYG error if your black box uses special input/output (I/O) cell resources such as double data rate (DDR) or LVDS. When using these special I/O resources, the resulting black box should directly drive a pin instead of an I/O atom. To prevent Synplify from inserting an I/O atom between your black box and the pin, please add the following line to the synthesis directive of your black box: "black_box_pad_pin = portname".

This will allow you to have Disable I/O Insertion = off globally and prevent Synplify from inserting I/O cells between the black box and the pin it is driving.

As an example:

module altddio_16_bidir (
datain_h,
datain_l,
inclock,
outclock,
aclr,
oe,
dataout_h,
dataout_l,
padio)/*synthesis syn_black_box black_box_pad_pin = "padio[15:0]"*/;

input [15:0]  datain_h;
input [15:0]  datain_l;
input   inclock;
input   outclock;
input   aclr;
input   oe;
output [15:0]  dataout_h;
output [15:0]  dataout_l;
inout [15:0]  padio;

endmodule

Note that /*synthesis syn_black_box */ indicates to Synplify that this module is a black box.

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