Article ID: 000084290 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Can Stratix II devices support differential HSTL and differential SSTL I/O standards on horizontal I/O pins?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Yes. This solution shows how to design for pseudo-differential HSTL and SSTL I/O standards for Stratix® II beginning with Quartus® II software version 4.2.

Pseudo-differential HSTL and SSTL has the following standards. There is a differential standard corresponding with each single-ended HSTL and SSTL standard.

Differential 1.5-V HSTL class I and II
Differential 1.8-V HSTL class I and II
Differential SSTL-18 class I and II
Differential SSTL-2 class I and II
 

Input pins

For input pins use the LVDS I/O standard assignment in Quartus II software to implement the differential input buffer.


Output pins

For output pins the negative pin should be manually inverted in the design file with the same I/O standard as the positive pin. Use the same internal signal that feeds the positive output pin but remember to invert the signal before feeding the negative output pin of the differential HSTL or SSTL output pair.

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