Issue 56899: Volume 1, Chapter 5 "Clock Networks and PLLs in the Cyclone III Device Family" version 4.0
Figure 5-2 incorrectly states remote clock cannot be used to feed the PLLs in note 3. Remote clocks are shown by the dashed lines between the dedicated CLK pins and the PLLs. Remote clocks can use dedicated clock paths as described in note 4, but they are not compensated paths.
Issue 40267: Volume 1, Chapter 10 "Hot-Socketing and Power-On Reset in the Cyclone III Device Family" version 3.3
Page 3 states "The 3.0-V tolerance control circuit permits the I/O pins to be driven by 3.0 V before VCCIO, VCC, and VCCA supplies are powered up, and it prevents the I/O pins from driving out when the device is not in user mode."
This is incorrect, Cyclone III devices are fully interoperable with 3.3V signaling. This sentence should say "The 3.3-V tolerance control circuit permits the I/O pins to be driven by 3.3V before VCCIO, VCC, and VCCA supplies are powered up, and it prevents the I/O pins from driving out when the device is not in user mode."
Issue 10005983, Volume 1, Chapter 12. IEEE 1149.1 (JTAG) Boundary-Scan Testing for the Cyclone III Device Family, Version 2.2
Page 12-5 states the Cyclone III device family can support 2.5-V or 3.3-V input levels for JTAG but can also support lower voltage levels. Cyclone III devices can support lower voltage levels when the device VCCIO is set below 2.5V, consult the download cable data sheet to determine the minimum supported voltages . You will be able to power up the VCC of the download cable with the supply from VCCIO.
Issue 35989: Volume 1, Chapter 6 "I/O Features in the Cyclone III Device Family" version 3.3
Page 4 describes the programmable slew rate control option and states "You cannot use the programmable slew rate feature when using OCT with calibration."
Programmable slew rate is also not available when using non-calibrated OCT. This sentence should say "You cannot use the programmable slew rate feature when using OCT with or without calibration."
Resolved issues:
Issue 379674: Volume 1, Chapter 9 “Configuration, Design Security, and Remote System Upgrades in Cyclone III Devices” version 1.2
The correct frequency for CLKUSR in Cyclone III devices is 40MHz during user mode.
In the Cyclone III handbook there is a section called "Overriding Internal Oscillator" which states that CLKUSR is 80MHz, this is incorrect and will be fixed in a future version of this handbook
Issue 10006410: Volumn 1, Chapter 9 “Configuration, Design Security, and Remote System Upgrades in Cyclone III Devices” version 1.2
The current stated specification for tSTATUS, tCF2ST1, tCF2CK applies only for Cyclone III devices.
The following is the correct specification for Cyclone III LS devices:
tSTATUS (nSTATUS low pulse width): MIN=300 usec; MAX = 800 usec
tCF2ST1 (nCONFIG to nSTATUS high): MAX = 800 usec
tCF2CK (nCONFIG high to first rising edge on DCLK): MIN = 800 usec
Issue 10006384: Vol.1, Ch. 9: Configuration, Design Security, and Remote System Upgrades in Cyclone III Devices, Version 1.2
tCF2ST1 (nCONFIG high to nStatus high) timing in relation to tCFG (nCONFIG pulse width)
The tCF2ST1(nCONFIG high to nSTATUS high) timing does not vary according to the tCFG (nCONFIG pulse width). After the nCONFIG is released high, the nSTATUS is released high within the tCF2ST1 maximum specification provided you do not hold the nSTATUS low externally.
The note associated with the respective table will be changed to say "This value is applicable if you do not delay configuration by externally holding the nSTATUS low."
Issue 10001752, Volume 2, Chapter 1 "Cyclone III Device Datasheet: DC and Switching Characteristics", Version 1.5.
Preliminary toggle rate information has been removed and replaced with I/O interface specifications in document version 3.1.
Issue 10005037, Volume 1, Chapter 9 "Configuration, Design Security, and Remote System Upgrades in Cyclone III Devices" Version 1.1
The MSEL pin settings for the Fast Passive Parallel (FPP) configuration scheme is incorrect in Table 9-7 for Cyclone® III LS devices. The correct MSEL pins setting for the FPP configuration scheme are:
Device |
MSEL[3..0] |
Configuration Voltage Standard |
Cyclone III |
1111 |
1.8/1.5 V |
Cyclone III LS |
0001 |
1.8/1.5 V |
The MSEL pin settings for other configuration schemes are not affected.