Article ID: 000084249 Content Type: Troubleshooting Last Reviewed: 08/18/2023

Why do I get the following error messages when simulating PCI Express® Hard IP core in Modelsim?

Environment

  • Arria® V Hard IP for PCI Express Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    # ERROR:          53584 ns Shared memory data miscompare at address: 00010404                                                 
    # ERROR: 53584 ns     Expected Data: 01                                                                              
    # ERROR: 53584 ns       Actual Data: 00                                                                              
    # ERROR: 53584 ns                                                                                                    
    # ERROR: 53584 ns Shared Memory Data Display:                                                                        
    # ERROR: 53584 ns Address  Data                                                                                      
    # ERROR: 53584 ns -------  ----                                                                                      
    # ERROR: 53584 ns 00010400 00000000 00000000 00000000 00000000 <===                                                  
    # ERROR: 53584 ns 00010410 00000000 00000000 00000000 00000000                                                       
    # ERROR: 53584 ns 00010420 00000000 00000000 00000000 00000000                                                       
    # ERROR: 53584 ns 00010430 00000000 00000000 00000000 00000000                                                       
    # FATAL: 53584 ns   Stopping simulation due to miscompare                                                            
    # FAILURE: Simulation stopped due to Fatal error!
    # FAILURE: Simulation stopped due to error!

    Resolution

    This error message is due to the PCI Express® Hard IP core was setting to Single DWord Completer mode with the 'Single DW Completer' option being checked.
    To simulate in Single DWord Completer mode, the user needs to open the driver file: altpcietb_bfm_driver_avmm.v and edit to:

    parameter RUN_TGT_MEM_TST = 1;
    parameter RUN_DMA_MEM_TST = 0;
    parameter AVALON_MM_LITE = 1;

    Related Products

    This article applies to 3 products

    Stratix® V GX FPGA
    Cyclone® V GX FPGA
    Arria® V GX FPGA