Article ID: 000084197 Content Type: Troubleshooting Last Reviewed: 08/03/2023

Why are ECO changes to the D3 Delay Chain 1 not implemented correctly?

Environment

  • Intel® Quartus® Prime Standard Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® II software version 14.0 and earlier, you may find that ECO changes to the D3 Delay Chain 1 are not implemented correctly. The change does not take effect, and no difference is seen in the timing netlist or in hardware.

    This problem affects Arria® V and Cyclone® V devices.

    Resolution

    To work around this problem, do not use the ECO flow to modify the D3 Delay Chain 1 setting.

    You can set the D3 Delay chain 1 value by using the D3_DELAY assignment and recompiling the design.

    This problem is scheduled to be fixed in a future release of the Quartus® II software.

    Related Products

    This article applies to 2 products

    Arria® V FPGAs and SoC FPGAs
    Cyclone® V FPGAs and SoC FPGAs