Article ID: 000084196 Content Type: Troubleshooting Last Reviewed: 08/04/2023

Can a single fPLL output be used as a transceiver reference clock and also drive logic within the fabric on Stratix® V GX, Arria® V GX, and Arria® V GZ devices?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

No, a single fPLL output cannot be used as a transceiver reference clock source and also drive logic within the fabric on Stratix® V GX, Arria® V GX, and Arria® V GZ devices.

Resolution

To use the same fPLL to drive logic in the FPGA fabric, you can enable another fPLL output to drive your FPGA logic.

Related Products

This article applies to 2 products

Arria® V FPGAs and SoC FPGAs
Stratix® V FPGAs

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