Critical Issue
If you configure the Arria 10 Hard IP for PCI Express IP core with Avalon-MM
interface or Avalon-MM DMA interface and with the Enable control register
access (CRA) Avalon-MM slave port parameter turned off, the
CraIrq_o
interrupt signal, and in Avalon-MM variations, the
RxmIrq_<n>
interrupt signals, should
not be visible at the top level. However, the signals are available.
This issue has no workaround. You can ignore these interrupt signals. This issue is fixed in version 15.0 of the Arria 10 Hard IP for PCI Express IP core.