In the Quartus® II software version 7.1, there are known issues with the ALTMEMPHY megafunction timing constraint files (in SDC format). These issues affect timing closure for Stratix® II designs implementing multiple memory controllers with the Use dedicated PLL clock outputs to drive memory clocks option enabled. To perform correct timing analysis for multiple DDR controllers (or ALTMEMPHY instantiations), add an extra SDC file to your project that correctly sets up the clocks for all the instantiations.
In the example below, a design has two DDR2/DDR High Performance Controller MegaCore® instances with wrapper names of core1 and core2. The MegaWizard® Plug-In Manager creates two files, core1_phy_ddr_timing.sdc and core2_phy_ddr_timing.sdc to constrain the memory interfaces. If your design instantiates the ALTMEMPHY megafunction directly (with your own controller), the file names will not include the _phy part of the file names.
The design requires a new SDC file called altemphy_general.sdc that contains the following constraints:
set pll_inclk *core1_phy_alt_mem_phy_sii_inst|clk|*|altpll_component|pll|inclk\[0\]
foreach_in_collection c [get_pins -compatibility_mode ] { }
set pll_ref_clk [get_node_info -name ]
create_clock -period 10.000
set pll_inclk *core2_phy_alt_mem_phy_sii_inst|clk|*|altpll_component|pll|inclk\[0\]
foreach_in_collection c [get_pins -compatibility_mode ] { }
set pll_ref_clk [get_node_info -name ]
create_clock -period 10.000
This example shows two instantiations of the controller/PHY. For your design, create a similiar SDC file that properly constrains the clocks. For each controller/PHY, change the name in the above SDC commands to match your instantiation name, and change the clock period in the create_clock line to match the period of the reference clock provided to the ALTMEMPHY megafunction. For designs with more than two instantiations, repeat the 4 lines that are required for each instance.