Article ID: 000084015 Content Type: Troubleshooting Last Reviewed: 08/03/2023

Why does my Arria® V design fail to route even though the device is not fully utilized?

Environment

  • Quartus® II Software
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® II software version 13.1 and earlier,  you may see that your Arria® V design fails to route when the device is not fully utilized. This problem occurs when a high fanout clock is incorrectly promoted to a regional clock net that restricts the placement of the destination logic to a quadrant of the device.

     

     

    Resolution

    To work around this problem, manually assign your clock to be global rather than regional using the assignment below:

    set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to "<clock name>"

     

    Related Products

    This article applies to 4 products

    Arria® V SX SoC FPGA
    Arria® V ST SoC FPGA
    Arria® V GX FPGA
    Arria® V GT FPGA