Article ID: 000083800 Content Type: Troubleshooting Last Reviewed: 09/11/2012

*** Fatal error: Module: quartus_fit.exe Exception: Access Violation Stack Trace: 08fa50e7: FSAC_OCT_MGR::place_atom() 0x7181 (FITTER_FSAC) 08fb7c98: FSAC_OCT_MGR::place_atom() 0x19d32 (FITTER_FSAC)

Environment

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Description

You may get the following fitter error in the Quartus® II software version 5.1 SP1 when targetting a Stratix® II GX device and your design has multiple ALT2GXB instances:

*** Fatal error: Module: quartus_fit.exe Exception: Access Violation
Stack Trace:
08fa50e7: FSAC_OCT_MGR::place_atom() 0x7181 (FITTER_FSAC)
08fb7c98: FSAC_OCT_MGR::place_atom() 0x19d32 (FITTER_FSAC)
08fb7af4: FSAC_OCT_MGR::place_atom() 0x19b8e (FITTER_FSAC)
08f9d86b: FSAC_CLOCK_MANAGER::check() 0x17 (FITTER_FSAC)
........
End-trace

This problem occurs when the calibration clock (cal_blk_clk) port of two or more ALT2GXB instances is driven by a synthesized clock from a PLL.

This problem is fixed in the Quartus II software version 6.0.  You can also contact Altera Applications for patch 1.08 for the Quartus II software version 5.1 SP1.

As a workaround in versions 5.1 and earlier, do the following: instead of feeding the cal_blk_clk ports of the ALT2GXB instances from a PLL, use the transceiver REFCLK signal for the calibration clock, as long as it is between 10 and 125 MHz. If your REFCLK frequency is not between 10 MHz and 125 MHz, use an I/O pin to feed the cal_blk_clk of the ALT2GXB instances and set its clock frequency between 10 MHz and 125 MHz.

Related Products

This article applies to 1 products

Stratix® II GX FPGA