Article ID: 000083753 Content Type: Troubleshooting Last Reviewed: 02/13/2006

Are there any known errors in AN 208: Configuring Stratix devices v1.0?

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BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description Yes, The MSEL pin connections in Figure 2 and 6 are incorrect. For Passive Serial configuration mode, the MSEL[1] pin should be connected to VCC, while MSEL[0] and MSEL[2] pins should be connected to GND. The correct information is listed in Table 2.

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Stratix® FPGAs