Why is the Quartus® II software applying the Cyclone® III M9K memory block read issue fix to memory instances that are not being reported as susceptible to bit error when applying the RAM Bit Reservation global fitter setting Auto, Standard, or Maximum?

During compilation, the Quartus® II software will analyze each memory instance and implement it in M9K block(s) with the widest data width that can fit that memory depth for optimal performance. If the RAM Bit Reservation setting has been applied globally to the design, this may result in the fix being applied to a narrow data width memory instance that is not susceptible to the M9K memory block read issue.
 
For example, for a logical memory instance that is dual-clock and 128x8 in size, the widest M9K configuration that can accommodate that memory is 256x36 mode.  The Quartus II software may choose such an implementation and subsequently apply the fix to that memory instance.  A memory instance implemented this way would not be susceptible to the M9K memory block read issue because, although the M9K is configured in x36 mode in this case, the number of switching bits (aggressors) is much less.
 
Therefore, the Script for analyzing Cyclone III M9K block read susceptibility (.tcl) will not report these memories as susceptible, and this is expected behavior.

You should refer to the files generated by the tcl script for an accurate assessment of which memory instances are susceptible to the M9K read issue.

If your design has sufficient available M9K resources, you can ignore this behavior when applying the RAM Bit Reservation setting globally. If, however, the available M9K resources are scarce in your design, then apply the RAM Bit Reservation only to memory instances that are reported as susceptible by the tcl script via the Assignment Editor.