Article ID: 000083332 Content Type: Error Messages Last Reviewed: 08/20/2013

Error: Clock Divider node - You may encounter the error in Cyclone® V and Arria® V transceiver devices if you not connected the outclk_0 port of your Transceiver PLL to the ext_pll_clk input port of the transceiver Native PHY in external PLL mode.

Environment

  • Quartus® II Subscription Edition
  • PLL
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Error: Clock Divider node 'inst|altera_xcvr_native_av:txcvr_top_inst|av_xcvr_native:gen_native_inst.av_xcvr_native_insts[0].gen_bonded_group_native.av_xcvr_native_inst|av_pma:inst_av_pma|av_tx_pma:av_tx_pma|av_tx_pma_ch:tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb' is not properly connected on the 'CLKCDRLOC' port.

    You may encounter the error above in Cyclone® V and Arria® V transceiver devices if you have not connected the outclk_0 port of your Transceiver PLL to the ext_pll_clk input port of the transceiver Native PHY when in external PLL mode.

    Related Products

    This article applies to 8 products

    Cyclone® V GT FPGA
    Arria® V ST SoC FPGA
    Arria® V GX FPGA
    Cyclone® V GX FPGA
    Arria® V SX SoC FPGA
    Cyclone® V SX SoC FPGA
    Cyclone® V ST SoC FPGA
    Arria® V GT FPGA

    Need more help?

    Contact support

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.