Error (10162): Verilog HDL Object Declaration error at <flile>(4616): can't declare implicit net "perstn_pin"

Locate the <your Qsys variation>/altera_pcie_a10_hip_150/synth/<your variation>_alterapcie_a10_hip_150_****.v file (where **** is a randomly generated series of characters) and make these changes:

At line 2026 add this reset synchroniser:
//=================================
// Reset synchronizer
//=================================
generate begin : g_rst_sync
   if ((interface_type_integer_hwtcl == 1) || (include_sriov_hwtcl == 1)) begin : g_syncrstn_avmm_sriov
         // Reset synchronizer
         altpcie_reset_delay_sync #(
            .ACTIVE_RESET           (0),
            .WIDTH_RST              (10),
            .NODENAME               ("app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl"),
            .LOCK_TIME_CNT_WIDTH    (1)
         ) app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl (
            .clk         (coreclkout_hip),
            .async_rst   (~reset_status),
            .sync_rst(app_rstn[9:0])
         );
   end
end
endgenerate

At line 4378, delete this reset synchroniser
// Reset synchronizer      
altpcie_reset_delay_sync #(      
   .ACTIVE_RESET           (0),      
   .WIDTH_RST              (10),      
   .NODENAME               ("app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl"),      
   .LOCK_TIME_CNT_WIDTH    (1)      
) app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl (      
   .clk         (coreclkout_hip),      
   .async_rst   (~reset_status),      
   .sync_rst(app_rstn[9:0])      
    );

At line 4612 change this line:
.power_on_reset_n           (perstn_pin

to this:
.power_on_reset_n           (app_rstn[0]

This problem is scheduled to be fixed in a future release of the Quartus® II software