Article ID: 000083127 Content Type: Troubleshooting Last Reviewed: 12/20/2011

Arria V Hard IP for PCI Express Should Return an Error When You Select the 64-Bit Interface for Gen1 x8 or Gen2 x4 Variants

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    You can specify a 64-bit Avalon Streaming (Avalon-ST) interface for the Gen1 x8 and Gen2 x4 Arria V Hard IP for PCI Express IP Cores in both the MegaWizard and Qsys design flows. However, the Gen1 x8 and Gen2 x4 variants require the 128-bit Avalon-ST interface.

    Resolution

    This issue is fixed in version 11.1 SP2 of the Arria V Hard IP for PCI Express IP Core.

    Related Products

    This article applies to 1 products

    Arria® V FPGAs and SoC FPGAs

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