Example error message:
# 25320 ns - tb.error ERROR #2: signal did not have expected value
# tb.expect signal Check valid write data
# expected 01110110010101000011001000010000
# got 11111110110111001011101010011000
# | || || || |
# tb.expect hexadecimal:
# expected 76543210
# got fedcba98
This is an error occurred due to an uninitialized RTL parameter in the IP functional simulation model. If you apply IO master/slave module in your logical layer, you may run into this issue. To solve this issue, you can regenerate the IP functional simulation model with the following procedure:
1. Open a command prompt and direct the path to your project directory.
2. Type the following command line to regenerate the IP Functional Simulation Model for DUT and SISTER with the quartus_map command line option SIMGEN_RAND_POWERUP_FFS=OFF:
quartus_map --simgen --simgen_parameter="CBX_HDL_LANGUAGE=Verilog,SIMGEN_RAND_POWERUP_FFS=OFF" --family=stratixiv \
--source="./rio_rio.v" \
--source="./rio_riophy_gxb.v" \
--source="./rio_phy_mnt.v" \
--source="./rio_riophy_xcvr.v" \
--source="./rio_riophy_dcore.v" \
--source="./rio_riophy_reset.v" \
--source="./rio_concentrator.v" \
--source="./rio_drbell.v" \
--source="./rio_io_master.v" \
--source="./rio_io_slave.v" \
--source="./rio_maintenance.v" \
--source="./rio_reg_mnt.v" \
--source="./rio_transport.v" \
rio.v
cp rio_rio_sister.v rio_sister_rio.v
cp rio_riophy_gxb_sister.v rio_sister_riophy_gxb.v
quartus_map --simgen --simgen_parameter="CBX_HDL_LANGUAGE=Verilog,SIMGEN_RAND_POWERUP_FFS=OFF" --family=stratixiv \
--source="./rio_sister_rio.v" \
--source="./rio_sister_riophy_gxb.v" \
--source="./rio_phy_mnt_sister.v" \
--source="./rio_riophy_xcvr_sister.v" \
--source="./rio_riophy_dcore_sister.v" \
--source="./rio_riophy_reset_sister.v" \
--source="./rio_concentrator_sister.v" \
--source="./rio_drbell_sister.v" \
--source="./rio_io_master_sister.v" \
--source="./rio_io_slave_sister.v" \
--source="./rio_maintenance_sister.v" \
--source="./rio_reg_mnt_sister.v" \
--source="./rio_transport_sister.v" \
rio_sister_rio.v
3. You need to modify the command line based on the correct device and HDL information.
Example: "CBX_HDL_LANGUAGE=Verilog" or "CBX_HDL_LANGUAGE=HDL"
"--family=Stratix® IV" or = one of "Arria® II GX, Cyclone® IV, Arria GX, Stratix II GX"
4. After the command, Quartus® will regenerate a new IP Functional Simulation Model file which is error-free.