Critical Issue
Due to a problem with the Intel® Quartus® Prime Software version 16.0 and above, the Intel® Arria® 10 FPGA Low Latency Ethernet 10G MAC's dynamically generated multi-rate design example has additional /-3.2 ns of error in 1588's accuracy. As a result, the total error may be larger than the user guide's claim, which is /-3 ns.
The following lists the affected multi-rate design example variants:
- 1G/10G Ethernet with 1588 Design Example (Intel Arria 10 FPGA)
- 10M/100M/1G/10G Ethernet with 1588 Design Example (Intel Arria 10 FPGA)
To work around this problem, follow these steps:
- For the Intel® Quartus® Prime Software v16.0, after the affected design example is generated, open the altera_eth_multi_channel_1588.sv file from this directory "<project_directory>\rtl" and modify the following lines:
localparam DEFAULT_NSEC_PERIOD_10G = 4'h3;
localparam DEFAULT_FNSEC_PERIOD_10G = 16'h3333; - For the Intel Quartus Prime Software v16.1 and above, after the affected design example is generated, from the Intel Quartus Prime Software menu, click Open and navigate to <project_directory>\rtl\altera_eth_1588_tod. Select altera_eth_1588_tod_10g.ip to launch the IP parameter editor of the Intel 10G 1588 Time-of-day module, and then update the following parameters:
DEFAULT_NSEC_PERIOD to 3
DEFAULT_FNSEC_PERIOD to 0x00003333
DEFAULT_NSEC_ADJPERIOD to 3
DEFAULT_FNSEC_ADJPERIOD to 0x00003333
This problem is fixed starting with the Intel® Quartus® Prime Pro/Standard Edition Software version 18.0.