Example Project Fails to Simulate When HardCopy Compatibility is Enabled for UniPHY External Memory Interfaces

The example project for designs generated with HardCopy Compatibility Mode enabled can fail to simulate.

The workaround for this issue is to modify two files, as follows:

1. In a text editor, open the file <variant_name>_example_design/simulation/<variant_name>_example_sim/ submodules/<variant_name>_example_sim_<variant_name>_example_sim.v
2. In the above file, change the line .INIT_FILE = (“dut_dut_e0_if0_p0_sequencer_rom.v”) to .INIT_FILE = (“<variant_name>_example_sim_<variant_name>_example_sim_e0_if0_p0_sequencer_rom.v”)
3. In a text editor, open the file <variant_name>_example_design/simulation/<variant_name>_example_sim.qsf
4. In the above file, add the following lines: set_global_assignment -name EDA_TEST_BENCH_FILE <variant_name>_example_sim/submodules/hc_rom_reconfig_gen.sv - section_id uniphy_rtl_simulation -hdl_version SystemVerilog_2005 and set_global_assignment -name SOURCE_FILE <variant_name>_example_sim/submodules/<variant_name>_example_sim_ <variant_name>_example_sim_e0_if0_p0_sequencer_rom.hex