Description
In the Quartus® II software version 15.0 Update 2 and earlier, you may receive this error when generating a Qsys testbench for the Altera Modular ADC IP core.
This error occurs because the ADC Avalon®-ST sink does not have a data port. The Avalon-ST source Bus Functional Model requires a data port width greater than 0.
Resolution
To avoid this error, only generate the simple testbench for Qsys systems that export this port.