Article ID: 000082926 Content Type: Troubleshooting Last Reviewed: 10/23/2015

Why does my Stratix IV device exhibit higher than expected VCC current draw during Fast Passive Parallel (FPP) configuration?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

When performing FPP configuration of EP4SGX180, EP4SGX230, EP4SGX290, EP4SGX360, EP4SGX530, EP4SE230, EP4SE360, EP4SE530, EP4SE820, EP4S40G2, EP4S40G5, EP4S100G2, EP4S100G3, EP4S100G4,  and EP4S100G5 Stratix® IV devices using a high DCLK frequency, certain uncommon bitstream patterns may result in the device exhibiting higher than expected VCC current draw during configuration. When this occurs, the device will fail to enter user mode after configuration, or will assert a CRC_ERROR upon entering user mode.

Resolution

Your system is not impacted if you do not observe the failure symptoms described above. Please contact Altera mySupport if you suspect your system is impacted by this issue.

Related Products

This article applies to 3 products

Stratix® IV GX FPGA
Stratix® IV GT FPGA
Stratix® IV E FPGA