Is there a problem with single ended input reference clock support in Stratix III and Stratix IV devices when using altlvds in Quartus II software version 9.1?

Yes, there is a problem with single ended input reference clock support in Stratix® III and Stratix IV devices when using altlvds in Quartus® II software version 9.1

The device datasheet shows support for both single ended and differential reference clocks in the High Speed I/O specifications. However, during compilation in Quartus II software version 9.1, the fitter overwrites the user assigned single ended clock I/O standard and creates a complement pin and converts it to the LVDS I/O standard.

This is fixed in Quartus II software version 9.1SP1.