FPGA Knowledge Base
The Intel® FPGA Knowledge Base page provides links to applicable articles that span a variety of FPGA related issues. Use the FILTER BY left navigation to refine your selection by device family and Intel® Quartus Prime Software edition and version. Additional page user instructions are located at the bottom of this page.
12014 Results
Why isn’t the o_rx_pcs_ready signal asserted in the simulation after applying the reset sequence for the F-tile Ethernet Altera® Hard IP with Auto-Negotiation and Link Training (AN/LT) enabled? You may see that the o_rx_pcs_ready signal will not be asserted in the simulation if you assert a reset sequencer for the F-tile Ethernet Altera® Hard IP with Auto-Negotiation and Link Training enabled before Link Training (LT) is completed on all lanes. If Link Training (LT) is enabled and is in progress, it should be completed at least once before performing any reset sequencer. |
01/17/2025 |
Why does the F-Tile JESD204C Altera® IP have the j204c_tx/rx_rst_ack_n signals not deassert properly even when tx/rx_rst_n signal has been deasserted and adhered to the F-Tile JESD204C Altera® IP TX/RX Reset Sequence in simulation? It is observed that the j204c_tx/rx_rst_ack_n acknowledgment reset signals are not deasserting (low -> high) and remain asserted at logic level ‘0’. This behavior is observed even after the user has deasserted the reset signals j204c_tx/rx_rst_n and j204c_tx/rx_rst_avs_n by following the F-Tile JESD204C Altera® IP TX1/RX2 Reset Sequence. |
01/17/2025 |
Why does the example design for Stratix® 10 10GBASE-KR PHY IP generated using the Quartus® Prime Pro Edition software version 24.3 and run in Questa*-Intel® FPGA or Starter Edition fail during simulation? Due to a problem in the Stratix® 10 10GBASE-KR PHY IP example design generated using the Quartus® Prime Pro Edition software version 24.3, the simulation fails for the Questa*-Intel® FPGA or Starter Edition simulators. |
01/17/2025 |
Why does the PHY Lite for Parallel Interfaces Altera® IP Parameter Editor GUI not produce any error message when input or bidirectional pins are placed in the same lane as RZQ using POD I/O standards? Due to a problem in Quartus® Prime Pro Edition Software version 24.3, you might see that the PHY Lite for Parallel Interfaces Altera® IP Parameter Editor GUI does not produce an error message when input or bidirectional pins are placed in the same lane as the RZQ pin, and the I/O standard is either 1.1-V POD or 1.2-V POD. |
01/14/2025 |
Is there a known Parallel Flash Loader II FPGA IP issue when configuring Agilex™ 7 FPGA series devices in Avalon-ST configuration mode? Yes, due to a problem with the Parallel Flash Loader II FPGA IP (PFL-II) in Quartus® Prime Standard Edition Software version 23.1 and earlier, you may see configuration fail with some bitstreams when configuring Agilex™ 7 series devices in Avalon-ST configuration mode. |
01/13/2025 |
Error(21843): Rule: gdrb_ip758fluxtop::ux0_cdr_postdiv_counter_range_rule @ gdr.z1577b.u_ux_quad_2.flux_top You may encounter this error during the Logic Generation stage when the F-Tile PMA/FEC Direct PHY Altera® IP is configured with a value for TX user clock div by: (fgt_tx_pll_txuserclk_div) or RX user clock div by: (fgt_rx_cdr_rxuserclk_div), such that the generated User Clock 1 value exceeds the maximum specification for the corresponding Agilex™ 7 device core frequency, as specified in the datasheet. |
01/09/2025 |
Why does the Agilex™ 7 F-Tile Ethernet Altera® Hard IP not correctly support unidirectional mode of operation for data rates other than 10GE, the Tx datapath is unusable when the Rx datapath link is broken or under reset? Due to a problem in the Quartus® Prime Pro Edition Software version 24.3 and earlier, the Agilex™ 7 F-Tile Ethernet Altera® Hard IP when configured to data rates other than 10GE with Link Fault Generation Option being set to Unidirectional does not correctly respond to local faults. The TX datapath is also unusable when the RX datapath link is broken or under reset. |
01/09/2025 |
Why does the F-Tile JESD204C Altera® IP Design Example fail to compile when migrated from a previous version of the Quartus® Prime Pro Edition Software to version 24.3? Due to a problem in the Quartus® Prime Pro Edition Software version 24.3, the F-Tile JESD204C Altera® IP Design Example will fail to compile when migrated from any previous version of the Quartus® Prime Pro Edition Software to version 24.3. |
01/09/2025 |
Why does the RX MAC of the F-Tile 25G Ethernet Altera® IP report FCS errors? Due to a problem in the Quartus® Prime Pro Edition Software version 23.2, you may see random FCS errors at the RX MAC of the F-Tile 25G Ethernet IP. |
01/09/2025 |
Why is the GTS PMA/FEC Direct PHY Altera® IP version 5.0.0 in the Quartus® Prime Pro Edition Software project generated with QPDS 24.2 not auto upgrading the IP to version 6.0.0 in version 24.3? The GTS PMA/FEC Direct PHY Altera® IP version 5.0.0 generated with version 24.2 is not auto upgrading to IP version 6.0.0 in 24.3 due to the changes in IP parameter values. |
01/09/2025 |
How can I assign an HVIO pin in Signal Probe? Due to a problem in the Quartus® Prime Pro Edition Design Software version 24.3 and earlier, Signal Probe status reports as "Unconnected" when assigning an HVIO pin on the Agilex™ 5 devices. |
01/03/2025 |
Can I route the Agilex™ 7 FPGA F-Series device out_refclk_fgt_[i] signal of the F-Tile Reference and System PLL Clocks FPGA IP to the FPGA core logic? No, you cannot route the Agilex™ 7 FPGA F-Series device out_refclk_fgt_[i] signal of the F-Tile Reference and System PLL Clocks FPGA IP to the FPGA core logic. Due to a problem in the Quartus® Prime Pro Edition Software version 24.3 and earlier, Quartus® Prime software will incorrectly compile designs that route the F-Tile Reference and System PLL Clocks FPGA IP out_refclk_fgt_[i] signal to the FPGA core logic. This signal is not intended for this purpose. |
12/26/2024 |
Why did compilation fail for the F-Tile Ethernet Multirate Altera® FPGA IP Design using a 400GE-4 or 400GE-8 reconfiguration group with partition assignments? In the F-Tile Ethernet Multirate Altera® FPGA IP GUI, if you choose the 400GE-4 (use FHT PMA) or 400GE-8 (use FGT PMA) reconfiguration group and put partition assignments as below, you might encounter compilation failure. |
12/20/2024 |
Why is the F-Tile Ethernet FPGA Hard IP with flow control enabled getting blocked from sending traffic when it receives PFC frames from a link partner? Due to a problem in the Quartus® Prime Pro Edition Software version 23.4 and earlier, the F-Tile Ethernet FPGA Hard IP with flow control enabled is blocked from sending traffic when it receives PFC (Priority-based Flow Control) frames from the link partner. |
12/19/2024 |
Why is the Integer Overflow fix removed in Intel® SOCEDS 18.1 Standard Version in Intel® SoC FPGA Embedded Development Suite (SoC EDS) 18.1 Release Notes? The Integer Overflow fix is patched in Intel® SoC FPGA Embedded Development Suite (SoC EDS) 18.1 Pro version. |
12/19/2024 |
Error(21843): engineered_link_mode == DISABLE (or) ENABLE Due to a problem in the Quartus® Prime Pro Edition Software version 24.3 and earlier, Agilex™ 7 F-Tile transceiver designs may fail during the compilation process when a TX Simplex F-Tile transceiver IP and RX Simplex F-Tile transceiver IP are merged within the same quad and channel but have different "engineered_link_mode" settings. |
12/18/2024 |
Why are the “rst_tx_stats” and the “rst_rx_stats” register bits not functioning correctly when using the F-tile Ethernet FPGA hard IP? Due to a problem in the Quartus® Prime Pro Edition Software version 24.2, the "rst_tx/rx_stats" register may not get cleared after reset. |
12/16/2024 |
Why are the PTP statistics registers showing incorrect values after reset using the F-Tile Ethernet FPGA Hard IP with PTP enabled? Due to a problem in the Quartus® Prime Pro Edition Software version 24.2 and later, when using the F-Tile Ethernet FPGA Hard IP with PTP enabled, the following registers might get reset to "1" instead of "0" after PTP statistics are cleared. |
12/16/2024 |
Why are errored packets (FCS errors, runts, fragments) observed using the F-Tile Ethernet FPGA Hard IP? Due to a problem in the Quartus® Prime Pro Edition Software version 24.2, asserting "force_rf" while Tx traffic is passing may cause the tx_data to start generating errored packets. |
12/16/2024 |
Why do I get unexpected output frequencies when issuing a mgmt_reset pulse before the first write operation during a dynamic reconfiguration of an Agilex™ 7 FPGA and SoC FPGA F/I-Series IOPLL? When performing an IOPLL dynamic reconfiguration of an Agilex™ 7 FPGA and SoC FPGA F/I-Series, you may get unexpected output frequencies if you do a write/read operation less than 4 clock cycles after a mgmt_reset pulse. This is because the internal circuitry of the IOPLL is in an initialization state, and it must wait at least 4 clock cycles for it to exit such a state. |
12/16/2024 |
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