Article ID: 000082265 Content Type: Troubleshooting Last Reviewed: 09/02/2012

Why does the DDR2 High Performance (HP) Controller simulation not show 400ns of delay from CKE going high to first Precharge (PCH) command even when I have specified the tINIT time of 200us?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

DDR2 HP Controller simulation does not show 200us of tINIT time as well as 400ns of delay from CKE going high to first PCH command even when you have specified the tINIT time of 200us if you have chosen "Quick Calibration" for "Auto Calibration Simulation Option" in the IP Megawizard of the DDR2 HP Controller. This is only a simulation behavior and will not show up in the hardware.

You should choose "Full Calibration (long simulation time)" If you want to wait for 400ns in the simulation as well.

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This article applies to 6 products

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Stratix® IV E FPGA

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