Article ID: 000082226 Content Type: Troubleshooting Last Reviewed: 01/27/2023

Why does the Intel® Arria 10® PCI Express* Hard IP lane error status register fail to clear?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem with the write address decoding for the Intel® Arria® 10 PCI Express* Hard IP, you may fail to clear the lane error status register after writing ‘1’ to this register.

     

     

    Resolution

    To work around this problem, write a ‘1’ to link control 3 registers (Offset 04h) located in the Secondary PCI Express* Extended Capability. This register will be set, and the lane error status register will be cleared.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs

    Need more help?

    Contact support

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.