By default, the Quartus® II software generates I/O models for all output and bidirectional pins in the design. In many cases, the I/O model can be used to simulate the input side of the I/O buffer for bidirectional configurations. In the simulation software, you can set the buffer to be input or output depending on which direction of the interface you are simulating.
However, when using options such as parallel on chip termination (OCT) with calibration on bidirectional pins, the I/O IBIS model will not include the calibration OCT option on the input buffer. To simulate the input portion of these bidirectional pins, you need to download the device IBIS models and replace the I/O model with the appropriate input model in the Quartus II software generated IBIS model.
For devices that are not yet available for download, you can perform the following steps in order to generate the parallel OCT IBIS models:
- Create a test input pin in the top level of the design. Assign the desired I/O standard and input termination to the test input pin and compile the project. Because the EDA Netlist Writer only generates the output buffer model on bidirectional pins, adding an input-only pin is required to generate the input parallel OCT model.
- Alternatively, create a simple test project with an input-only pin and assign the desired I/O standard and input termination to generate the parallel OCT model.