Article ID: 000081126 Content Type: Troubleshooting Last Reviewed: 03/28/2023

In the Platform Designer, why are the Triple Speed Ethernet IP core clock names not described in the user guide?

Environment

  • Quartus® II Subscription Edition
  • Triple-Speed Ethernet Intel® FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The Triple Speed Ethernet User Guide describes the clock names used in the parameter editor configuration.

     

    The Platform Designer uses the following clock names:

     

    • control_port_clock_connection
    • pcs_mac_tx_clock_connection
    • pcs_mac_rx_clock_connection
    • receive_clock_connection
    • transmit_clock_connection
    Resolution

    The following Platform Designer clock names are equivalent to the clock names in the parameter editor:

    • control_port_clock_connection -> clk
    • pcs_mac_tx_clock_connection -> tx_clk
    • pcs_mac_rx_clock_connection -> rx_clk
    • receive_clock_connection -> ff_rx_clk
    • transmit_clock_connection -> ff_tx_clk

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