Article ID: 000081033 Content Type: Troubleshooting Last Reviewed: 08/14/2014

Why are bidirectional mem_dbi_n ports created when the 'Enable DM Pins' option is selected in the Arria 10 DDR4 controller?

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You may see bidirectional mem_dbi_n ports exposed when you create an Arria® 10 DDR4 controller with the 'Enable DM pins' options selected inside the IP Catalog GUI.

    In DDR4, the data mask (DM) and data bus inversion (DBI) features share the same pins, but cannot be enabled at the same time. When the DM or DBI feature is selected, the bidirectional mem_dbi_n ports will be exposed.

    Resolution

     

    Related Products

    This article applies to 3 products

    Intel® Arria® 10 GT FPGA
    Intel® Arria® 10 GX FPGA
    Intel® Arria® 10 SX SoC FPGA

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