Description
The FPGA JTAG does not require an external clock source other than TCK clock. However the HPS JTAG requires an external clock source derived from the EOSC1 pin. The Debug Access Port (DAP) uses the dbg_clk generated from the clock when controlling the HPS JTAG.
Resolution
To resolve this issue ensure the EOSC1 pin has an external clock source, and set the clock manager to supply the dbg_clk to the DAP.