Description
The XCVR_REFCLK_PIN_TERMINATION, DC_COUPLING_INTERNAL_100_OHM assignment fails in the Quartus® Ii software version 12.0 due to an error in the Transceiver PHY Intel® FPGA IP User Guide.
"Table 6-4. Transceiver and PLL Assignments for Stratix® V Devices" of the transceiver PHY IP userguide details the constraint as"DC_COUPLING_INTERNAL_100_OHM". The correct constraint is "DC_COUPLING_INTERNAL_100_OHMS"
Resolution
This error has been fixed in the Quartus® II software v12.0.