Article ID: 000080827 Content Type: Troubleshooting Last Reviewed: 12/20/2022

Why does the Avalon®-MM Intel® Stratix® 10 Hard IP for PCI* Express IP's dynamically generated design example fail timing on Intel® Stratix® 10 ES1 and ES2 devices?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem with the Intel® Quartus® Prime Pro Ediiton Software version 18.0 and 18.1, the Avalon®-MM Intel® Stratix® 10 Hard IP for PCI Express IP's dynamic generated design example fails static timing analysis.

    Resolution

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 18.1.1.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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