Article ID: 000080820 Content Type: Troubleshooting Last Reviewed: 01/03/2017

Why does the Stratix 10 Hard IP for PCI Express, configured in Gen3 mode, enter Recovery state several times when changing speed to Gen3?

Environment

  • Intel® Quartus® Prime Pro Edition
  • PCI Express
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    The Stratix® 10 L-Tile Hard IP for PCI Express® core configured in Gen3 mode may undergo several Recovery cycles when changing speed to Gen3.  After a few Recovery cycles, the link stabilizes in the L0 state.  Initial link up to Gen3 is not affected. The Recovery cycles only occur in subsequent speed changes after initial link training to Gen3.

    Resolution

    This issue is not fixed in L-Tile.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

    Need more help?

    Contact support

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.