Critical Issue
Description
This problem affects DDR3 products.
Quarter-rate DDR3 designs targeting Arria V devices and running at 667 MHz may not meet timing requirements on the address and command and read capture paths.
Resolution
The workaround for this issue is to add the following constraint to the SDC file:
if {} { foreach { ck_pin } { set_clock_uncertainty -from [get_clocks ] -to [get_clocks ] -add -hold 0.200 }}
In addition, 800 MHz speed grade memory components are recommended.
This issue will be fixed in a future release.