Under what conditions might the Deterministic Latency PHY fail to achieve rx_syncstatus when implementing the OBSAI protocol in Arria® V GZ and Stratix® V devices?

When implementing the OBSAI protocol using the Deterministic Latency PHY in Arria® V GZ and Stratix® V devices, you may fail to achieve rx_syncstatus when IDLE, IDLE_ACK and IDLE_REQ patterns are sent during the link up process. You can achieve synchronization by retriggering rx_patternalign or asserting rx_digitalreset.

This applies to the Deterministic Latency PHY with the following configuration:

• Data Rate: 6.144 Gbps or 3.072 Gbps
• PMA-PCS Data Width: 20-bits

To work around this problem, follow these steps:

For Quartus® II software versions before release 14.0:

1. File an Intel PreSales Support to obtain a software patch(patch0.87).
2. After the patch is installed, add the following assignment to your Quartus II Settings File (.qsf).
   set_global_assignment -name VERILOG_MACRO "SV_XCVR_CUSTOM_NATIVE_ASSERT_SYNC_STATUS_IMM=\"assert_sync_status_imm\""
3. Regenerate the Deterministic Latency PHY IP.
4. Recompile your design.

For Quartus II software versions 14.0 and later:

1. Add the following assignment to your .qsf file.
   set_global_assignment -name VERILOG_MACRO "SV_XCVR_CUSTOM_NATIVE_ASSERT_SYNC_STATUS_IMM=\"assert_sync_status_imm\""
2. Regenerate the Deterministic Latency PHY IP.
3. Recompile your design.
4. If you are implementing both the CPRI and OBSAI protocols in a single device, open an Intel PreSales Support for further support