Description
Due to a problem in the Intel® Quartus® Prime Software version 18.1 Update 1 and earlier, you may see the Warning message for unbound component 'MY_UART_TESTIP_RS232_0' in simulator log file while running simulation for RS232 UART IP with simulation files generated in VHDL. This is due to missing some IP files for simulation.
Resolution
To work around this problem select Verilog while generating the RS232 UART IP simulation files in Platform Designer.