Why does my HDMI Example Design IOPLL fail to lock on Intel® Arria® 10 and Intel Cyclone® 10 GX devices when generated using Intel Quartus® Prime versions 18.1.1 and earlier?

Due to a bug in the HDMI Example Design generated with Intel Quartus Prime versions 18.1.1 and earlier, the IOPLL may fail to lock for incoming TMDS clock frequencies between 171Mhz and 340MHz on Intel Arria 10 and Cyclone 10 GX devices.

To fix this problem you can open the following files and edit them as shown below.

\hdmi_0_example_design\rtl\reconfig_mgmt\mr_rom_pll_valuemask_8bpc.v

\hdmi_0_example_design\rtl\reconfig_mgmt\mr_rom_pll_valuemask_10bpc.v

\hdmi_0_example_design\rtl\reconfig_mgmt\mr_rom_pll_valuemask_12bpc.v

\hdmi_0_example_design\rtl\reconfig_mgmt\mr_rom_pll_valuemask_16bpc.v

Change from this

// ROM OFFSET 4 (171MHz - 340MHz)

… 

ROM[33] <= 32'h00000010; // cp

ROM[34] <= 32'h000000C0; // bw

To this

// ROM OFFSET 4 (171MHz - 340MHz) 

… 

ROM[33] <= 32'h0000000B; // cp

ROM[34] <= 32'h00000080; // bw

\hdmi_0_example_design\software\tx_control\xcvr_gpll_rcfg.c

Change from this

case 4: // <340MHz

…

else

GPLL_RCFG_WRITE(0xC2, 0x00000808); // c2 16

GPLL_RCFG_WRITE(0x20, 0x00000010);                            // cp

GPLL_RCFG_WRITE(0x40, 0x000000C0);                            // bw

To this

case 4: // <340MHz

…

else

GPLL_RCFG_WRITE(0xC2, 0x00000808); // c2 16

GPLL_RCFG_WRITE(0x20, 0x0000000B);                            // cp

GPLL_RCFG_WRITE(0x40, 0x00000080);                            // bw

This problem will be fixed in a future version of the Intel Quartus Prime generated Arria 10 and Cyclone 10 GX HDMI Example Designs.