If you are connecting PLL reference clock from a PLL output or a non-dedicated clock pin in your Arria® 10 design, additional jitter will be introduced. This jitter can be compensated for by adding a 100ps clock uncertainty constraint at the output clocks of the downstream PLL in the design.
Please refer to the following document for the details of applying the clock uncertainty constraint.
Arria® 10 PLL Cascading or Non-dedicated Clock Path Workaround Guideline
When upgrading design to Quartus Prime software v17.1 or later, the previously added constraints need to be revised:
a) if the existing clock uncertainty only comes from derive_clock_uncertainty set_clock_uncertainty -add -to <clock x> -from <clock y> 0.1 <Remove>
b) if the existing clock uncertainty comes from derive_clock_uncertainty additional “set_clock_uncertainty -add” v17.0: set_clock_uncertainty -add -to <clock x> -from <clock y> [expr <existing_value> 0.1] v17.1 or later: set_clock_uncertainty -add -to <clock x> -from <clock y> <existing_value>
c) if derive_clock_uncertainty is overridden by “set_clock_uncertainty” (no -add) - No change, need to keep the existing constraint set_clock_uncertainty -to <clock x> -from <clock y> [expr <existing_value> 0.1]
If the affected downstream PLL is Arria 10 PHYLite IOPLL, refer following steps for the details of applying the clock uncertainty constraint.
Starting with Quartus Prime software version 17.0, the “Use core PLL reference clock connection” is no longer visible in the Arria 10 Altera PHYLite IP parameter editor. The recommended way is to use dedicated clock pin to connect it to PHYLite IOPLL reference clock. If your design requires to use this feature, please read the following guidelines carefully and abide to them.
To enable the “Use core PLL reference clock connection” (Quartus Prime software version 17.0 and later), please add the below INI in the quartus.ini file.
ip_altera_phylite_en_pll_core_ref_ck = on
a2t_allow_cascaded_pll_in_cpa_compensation=on
When connecting PLL reference clock from a PLL output or a non-dedicated clock pin, additional jitter will be introduced.
For design implemented with Arria 10 Altera PHYLite version 17.0 and prior, this jitter can be compensated by adding 100ps clock uncertainty constraint at the output clocks of the downstream PLL in the design.
Add the following constraints for the clock uncertainty in the PHYLite generated SDC file for Quartus Prime Software version 17.0 and earlier. You will need to make the following changes every time you regenerate the Altera PHYLite IP.
1. Assign 100ps value to variable name additional jitter.
set additional_jitter 0.000
# First determine if a reference clock has already been created (i.e. Reference clock sharing)
if {$var(PLL_USE_CORE_REF_CLK) == "false"} {
set ref_clock_exists [ phy_altera_phylite_arch_nf_171_flagyzi_does_ref_clk_exist $pins(pll_ref_clock)]
if { $ref_clock_exists == 0 } {
# This is the reference clock used by the PLL to derive any other clock in the core
create_clock -period $ref_period -waveform [ list 0 $ref_half_period ] $pins(pll_ref_clock) -add -name ${inst}_ref_clock
}
} else {
set additional_jitter 0.100
}
2. Add additional clock uncertainty on the write FIFO clock:
set i_wf_clock 0
foreach_in_collection wf_clock $write_fifo_clk_neg {
set vco_clock_id [phy_altera_phylite_arch_nf_171_flagyzi_get_vco_clk_id $wf_clock var]
if {$vco_clock_id == -1} {
post_message -type critical_warning "Failed to find VCO clock"
} else {
set local_wf_clk_grp_${i_grp_idx}_${i_wf_clock} [ phy_altera_phylite_arch_nf_171_flagyzi_get_or_add_generated_clock \
-target [get_node_info -name $wf_clock] \
-name "${inst}_wf_clk_grp_${i_grp_idx}_${i_wf_clock}_neg" \
-source [get_node_info -name $vco_clock_id] \
-multiply_by 1 \
-divide_by [expr $var(PLL_VCO_TO_MEM_CLK_FREQ_RATIO)] \
-phase 180 ]
}
incr i_wf_clock
}
#new constraint:
if {$additional_jitter != 0} {
set_clock_uncertainty -to [get_clocks ${inst}_wf_clk_grp_*] -add $additional_jitter
}
3. Add additional clock uncertainty on the write path:
if {[llength $write_clocks]>0} {
# We don't need derive_clock_uncertainty numbers because we have include FLS JITTER in set_output_delay
set_clock_uncertainty -to [get_clocks $write_clocks] [phy_altera_phylite_arch_nf_170_zul23qq_round_3dp [expr 0.5*($var(WR_SSO) $var(WR_JITTER_SCALED)) $additional_jitter ]]
}
4. No change on the read_clocks
if {[llength $read_clocks]>0} {
# We don't need derive_clock_uncertainty numbers because we have include FLS JITTER in set_input_delay
set_clock_uncertainty -to [get_clocks $read_clocks] 0.0
}
5. Add additional clock uncertainty on c2p/p2c transfers (phy_clk <->usr_clock)
if {$i_phy_clock > $same_tile_index} {
# C2P/P2C where the periphery tile != CPA tile.
# For these transfers the SDC explicitly overrides the clock uncertainty values.
# Therefore, when overconstraining we must not use the "-add" option.
set add_to_derived ""
set c2p_su [expr {$p2c_c2p_multi_tile_clock_uncertainty [lindex $periphery_overconstraints 0] [lindex $periphery_clock_uncertainty 0]} additional_jitter]
set c2p_h [expr {$p2c_c2p_multi_tile_clock_uncertainty [lindex $periphery_overconstraints 1] [lindex $periphery_clock_uncertainty 1]} additional_jitter]
set p2c_su [expr {$p2c_c2p_multi_tile_clock_uncertainty [lindex $periphery_overconstraints 2] [lindex $periphery_clock_uncertainty 2]} additional_jitter]
set p2c_h [expr {$p2c_c2p_multi_tile_clock_uncertainty [lindex $periphery_overconstraints 3] [lindex $periphery_clock_uncertainty 3]} additional_jitter]
} else {
# C2P/P2C where the periphery tile == CPA tile
# For these transfers it is safe to use the -add option since we rely on
# derive_clock_uncertainty for the base value.
set add_to_derived "-add"
set c2p_su [expr [lindex $periphery_overconstraints 0] [lindex $periphery_clock_uncertainty 0] additional_jitter/2]
set c2p_h [expr [lindex $periphery_overconstraints 1] [lindex $periphery_clock_uncertainty 1] additional_jitter/2]
set p2c_su [expr [lindex $periphery_overconstraints 2] [lindex $periphery_clock_uncertainty 2] additional_jitter/2]
set p2c_h [expr [lindex $periphery_overconstraints 3] [lindex $periphery_clock_uncertainty 3] additional_jitter/2]
}
6. Add additional clock uncertainty within core transfer (usr_clock/extra core clock <->usr_clock/extra core clock)
set c2c_same_su [expr [lindex $core_overconstraints 0] [lindex $core_clock_uncertainty 0] additional_jitter]
set c2c_same_h [expr [lindex $core_overconstraints 1] [lindex $core_clock_uncertainty 1]]
set c2c_diff_su [expr [lindex $core_overconstraints 2] [lindex $core_clock_uncertainty 2] additional_jitter]
set c2c_diff_h [expr [lindex $core_overconstraints 3] [lindex $core_clock_uncertainty 3] additional_jitter]
foreach src_core_clock_local $core_clocks_local {
if {$src_core_clock_local != ""} {
foreach dst_core_clock_local $core_clocks_local {
if {$dst_core_clock_local != ""} {
if {$src_core_clock_local == $dst_core_clock_local} {
# Same clock network transfers
set_clock_uncertainty -from $src_core_clock_local -to $dst_core_clock_local -setup -add $c2c_same_su
set_clock_uncertainty -from $src_core_clock_local -to $dst_core_clock_local -hold -enable_same_physical_edge -add $c2c_same_h
} else {
# Transfers between different core clock networks
set_clock_uncertainty -from $src_core_clock_local -to $dst_core_clock_local -setup -add $c2c_diff_su
set_clock_uncertainty -from $src_core_clock_local -to $dst_core_clock_local -hold -add $c2c_diff_h
}
}
}
}
}
7. For user logic that involves user_created_clock and PHYLite output clock, user will need to add the extra 100ps clock uncertainty on that clock transfer path in the user sdc file.
8. Report SDC and check in the SDC Assignments>Set Clock Uncertainty report, make sure the extra 100ps is added into the affected clock transfer paths
9. Retime or recompile the design and ensure timing closure
10. Perform rigorous hardware testing to ensure design is working properly before going into production
When upgrading design to Quartus Prime software v17.1 or later:
a) Launch IP Upgrade Tool to upgrade the Arria 10 Altera PHYLite IP to v17.1
b) The generated PHYLite SDC file will have all the necessary clock uncertainty added when core PLL reference clock is used.
c) The extra 100ps clock uncertainty added for user logic path that involves user_created_clock and PHYLite output clock previously will require to remain in the user sdc file.
d) Perform full compilation on the design and ensure timing closure.