Article ID: 000080281 Content Type: Troubleshooting Last Reviewed: 12/16/2014

VHDL PIPE Simulation Failure for PCI Express in Stratix IV Devices

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    PIPE simulations of PCI Express in Stratix IV devices fail. A descrepancy between the definition of eidle_infer_sel signal in the PCI Express IP core and in altpcie_hip_pipen1b_qsys causes the failure. eidle_infer_sel is defined as a 12-bit vector in the IP core and 24 bits in altpcie_hip_pipen1b_qsys.

    Resolution

    The workaround is to simulate in serial mode.

    Related Products

    This article applies to 1 products

    Stratix® IV FPGAs

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