Do Stratix IV devices support a single ended reference clock for LVDS receivers (altlvds)?

Yes, Stratix® IV devices support single ended reference clocks for the altlvds receiver rx_inclock port. There are two different maximum single ended reference clock frequency specifications based on the configuration of the altlvds receiver:

1) DPA and Soft-CDR mode
The specifications are same as the differential reference clock frequency specifications

2) Source synchronous (non-DPA) mode
The specifications are lower than the differential reference clock frequency specifications.

The updated specifications are available beginning in the Stratix IV Device Datasheet (PDF) version 4.0.