Article ID: 000080016 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Do I have access to the memory locations used to store the write data pattern used in calibration for DDR, DDR2, DDR3 High performance Controller or Altmemphy in the user mode?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Memory bank 0, row 0, and column addresses 0 to 55 store calibration data. You have access to these memory locations in the user mode.

If you reset the controller the calibration process starts again and you will lose the data in the above mentioned memory locations because the calibration data will again get re-written.

Related Products

This article applies to 8 products

Cyclone® III FPGAs
Arria® GX FPGA
Stratix® II GX FPGA
Stratix® II FPGAs
Stratix® IV GX FPGA
Stratix® III FPGAs
Arria® II GX FPGA
Stratix® IV E FPGA

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