Article ID: 000079968 Content Type: Troubleshooting Last Reviewed: 04/25/2023

Under what conditions might the Deterministic Latency PHY fail to achieve rx_syncstatus when implementing the OBSAI protocol in Cyclone® V devices?

Environment

  • Quartus® II Software
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    When implementing the OBSAI protocol using the Deterministic Latency PHY in Cyclone® V devices, you may fail to achieve rx_syncstatus when IDLE, IDLE_ACK, and IDLE_REQ patterns are sent during the link-up process. You can achieve synchronization by retriggering rx_patternalign or asserting rx_digitalreset.

     

    Resolution

    This applies to the Deterministic Latency PHY with the following configuration.

    • Data Rate: 3.072 Gbps
    • PMA-PCS Data Width: 20-bits 

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    Related Products

    This article applies to 4 products

    Cyclone® V SX SoC FPGA
    Cyclone® V GT FPGA
    Cyclone® V GX FPGA
    Cyclone® V ST SoC FPGA

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