Article ID: 000079783 Content Type: Troubleshooting Last Reviewed: 04/11/2023

Cyclone® V SoC Pin-Out Table: Known Issues

Environment

  • Intel® Quartus® Prime Design Software
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Issue 95669: In the Cyclone® V SoC (SE, ST, and SX) pin-out files with Revision 1.1 and lower, the SD/MMC clock pins are incorrectly labeled. You will notice the name mismatch between the pin-out file and Cyclone V Device Family Pin Connection Guidelines (PDF).  In the Pin Connection Guidelines, the clock pins are named SDMMC_FB_CLK_IN and SDMMC_CCLK_OUT. However, the pin-out file uses the outdated name SDMMC_CLK_IN and SDMMC_CLK.

    When you cross-reference the pin names from the pin-out file to PCG, relate SDMMC_CLK_IN to SDMMC_FB_CLK_IN and SDMMC_CLK to SDMMC_CCLK_OUT.

    Resolution

    .

    Related Products

    This article applies to 4 products

    Cyclone® V ST SoC FPGA
    Cyclone® V SE SoC FPGA
    Cyclone® V FPGAs and SoC FPGAs
    Cyclone® V SX SoC FPGA