I compiled my design and it worked in the lab. I’ve re-compiled the same RTL in the same version of Quartus® II software and it doesn’t work. What could be wrong?

Check the following common trouble areas which can affect a design that can be impacted by marginal changes:

1. Analog Phenomenon:

·         Power & ground not within specification

·         Insufficient decoupling

·         Noise / Signal Integrity

2. Timing Constraints

·         Incomplete constraints

·         Inaccurate constraints

·         Poor timing exception constraints

3. Improper handling of async interfaces

·         Use Design Assistant to verify your design – You can find useful information to help resolve problems

·         Reset structures

·         Asynchronous clock domain transfers

·         Asynchronous signals