Why does my PCIe link get stuck in the Detect state for the Avalon® memory mapped interface in a Cyclone® IV device?

Due to a problem in the Cyclone® IV FPGA PCIe Hard IP PMA, the link might be stucked in the Detect.Active state.

This is because the transceiver receiver detect logic is not returning a PHYSTATUS pulse on the PIPE interface to the Hard IP core if the low period of two consecutive TxDetectRx is less than 544 ns.

Manually change the Hard IP reset logic to assert the crst and srst signal for at least 1 us.

You can use the following files to view the changes required for the Avalon® memory mapped interfaces to satisfy the requirement above.

• pcie_compiler_0 (.v) : Added reset logic can be found on multiple lines using the keyword new. Put these lines in your instantiation file for Avalon memory mapped interfaces.
• pcie_compiler_0 (.vhd): Added reset logic can be found on multiple lines using the keyword new. Put these lines in your instantiation file for Avalon memory mapped interfaces.

This problem has been fixed in Platform Designer implementations of the Cyclone IV PCIe Hard IP.