The Altera® PLL mega function, with dynamic phase shift ports enabled, may fail to lock if the scanclk input is not toggling when the refclk input starts toggling in simulation. In this case, the locked output signal and the output clocks will be stuck low.
You may also receive the following message if you are using ModelSim:
"# ** Error: (vsim-8630) nofile(-1): Infinity results from division operation."
This is due to a problem in the simulation model and does not represent the actual behavior of the device where the scanclk input may be free running.
Ensure that the scanclk input is set to logic 1 when not toggling.