Description
The Stratix IV® Hard IP for PCI Express® in VHDL has an inconsistency from its Verilog HDL counterpart. This inconsistency can cause errors in a PCIe design for certain addresses on the TX interface.
Resolution
In altpcierd_write_dma_requester_128.vhd at line 1036 change:
tx_desc_addr <= tx_desc_addr_pipe;
to
tx_desc_addr <= tx_desc_addr tx_length_byte_32ext;