Description
Yes, the reference clock needs to be stable before ATX PLL calibration is performed on Stratix® V GX/T and Arria® V GZ devices. ATX PLL calibration is automatically performed after device configuration.
Resolution
If the transceiver reference clock is not stable during ATX PLL calibration, the calibration may fail. To manually restart ATX PLL calibration, you should use the Avalon Memory Mapped register space within the Transceiver Reconfiguration Controller.
Please see the ATX PLL calibration section of the Transceiver PHY IP User Guide for more details on these registers.