Article ID: 000079491 Content Type: Troubleshooting Last Reviewed: 10/29/2012

Why signal fixedclk_locked is not in the port list?

Description

In the Stratix®  V Hard IP PCIe core v12.0, the fixedclk is driven by Serdes reference clock input ref_clk directly, so the signal fixedclk_locked signal is removed from the port list.

 

Resolution

 

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